Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing - Computers and Digital Techniques [see also IEE Proceedings-Computers and Digital Techniques], IEE

The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-eficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application to mapping a variety of processor geometries onto specific array networks. The layout algorithms are expressed in a new notational language, which is amenable to cellular layout in contrast to classical procedural languages. The layout technique is illustrated with both well known parallel-processing array networks and a new fault-tolerant square mesh with reconfigurable processors and interconnect. The square mesh with redundant processors provides high yield and operational reliability.